System-on-chip (SoC) integration on CMOS within wireless systems, in conjunction with the ongoing CMOS shrinkage path, requires appreciable redesign in order to accommodate industry goals. This is especially true for radio frequency (RF) and some analog devices. The result of the continuous march toward integration and miniaturization is that architectures require increased digital circuitry and a reduction in purely analog sub-systems.
Multi-modal radios and other wireless devices present their own challenges in regard to the foregoing paradigm. In particular, respective developments for receivers, synthesizers and transmitters are needed to optimize overall system design. Additional goals in this regard include area savings and reduced current and power consumption. In short, improved SoC design is desirable as applied to wireless and other devices.
Illustrative Background Structures
FIG. 1 shows a transmitter structure (transmitter) 100 in accordance with known techniques. The transmitter 100 shows one approach using polar modulator architecture. The structure 100 includes in-phase-and-quadrature (IQ) to polar conversion circuitry (i.e., or a sub-system) 102. The IQ subsystem 102 receives an in-phase modulation (i.e., intelligence) signal at an input 104 and a quadrature modulation signal at an input 106. The in-phase and quadrature modulation signals are understood to be orthogonal to one another. The IQ subsystem 102 is capable of deriving distinct phase (i.e., angular degrees) and magnitude (i.e., absolute value) signals from the in-phase and quadrature modulation signals. An illustrative magnitude signal S1 is depicted in FIG. 1. Such derived phase-and-magnitude representation of modulation signals is also referred to as polar modulation.
Once the IQ subsystem (i.e., polar modulator) 102 derives the phase and magnitude signals, the phase information is modulated onto a carrier signal 108 by way of time derivative function block 110 and adder 112. A digital phase-lock loop (PLL) 114, being controllably influenced by the modulated carrier signal from adder 112, in turn controls an analog local oscillator (LO) 116. The LO 116 output signal is input to an IQ generator 118, which serves to provide in-phase and quadrature signals corresponding to the modulated carrier signal. Herein, the difference between such in-phase and quadrature signals is generally referred to as a differential signal.
The transmitter 100 also includes a digital-to-analog converter (DAC) 120. The DAC 120 is configured to receive the magnitude signal from the IQ subsystem 102, in digital signal form, and derive a corresponding analog magnitude signal. The analog magnitude signal and the differential signal are mixed at a mixer 122, power amplified by a driver 124 and coupled to one or more antennas 126.
It is noted that within the architecture of transmitter 100, the magnitude (i.e., amplitude) signal S1 is introduced directly to the mixer 122 prior to the driver (i.e., final amplifier) 124 stage. Under this polar modulation structure, especially for a digital implementation, the magnitude signal is always positive (i.e., of consistent polarity) and therefore the current through the mixer (e.g., the mixer 122) is changing with the magnitude without using a steady D.C. (direct current) current draw. This situation corresponds, generally, to class-B operation and shows favorable efficiency.
One challenge in using polar modulation architecture is establishing and maintaining proper synchronism between the phase and magnitude signals. This challenge is becoming more daunting as modulation bandwidths (i.e., information content per unit time) continue to increase in the industry. Illustrative narrowband systems like GSM and Bluetooth are such that polar modulation can be effectively applied without huge efforts. However, other protocols such as W-CDMA (i.e., Wideband Code Division Multiple Access) have requirements that are difficult to achieve. Other system protocols, such as WLAN (i.e., Wireless Local Area Network—IEEE 802.11 standard) or WiMax, have a bandwidth greater than 5 MHz and the respective requirements are extremely difficult to fulfill in mass production or necessitate incredible alignment efforts.
FIG. 2 shows another transmitter 200 in accordance with known techniques. The transmitter 200 includes functional elements (i.e., circuits, or sub-systems) that are analogous to respective elements within the transmitter 100, including a digital phase-lock loop 214, a local oscillator 216, and an IQ generator 218. Transmitter 200 further includes in-phase input node 204 and quadrature input node 206, respectively coupled to in-phase modulation signal S2 and quadrature modulation signal S3.
However, transmitter 200 does not include a polar modulator as was utilized by transmitter 100. Rather, transmitter 200 includes respective DACs 210 and 212. The DAC 210 is configured to receive the in-phase modulation signal from node 204, in digital signal form, and derive a corresponding analog in-phase signal. The analog in-phase signal from the DAC 210 is then mixed with a differential signal provided by the IQ generator 218 using a mixer 220. The mixed signal from mixer 220 is then routed to an adder 222.
In turn, the DAC 212 is configured to receive the quadrature modulation signal from node 206, in digital signal form, and derive a corresponding analog quadrature signal. The analog quadrature signal from the DAC 212 is then mixed with the differential signal provided by the IQ generator 218 using a mixer 224. The mixed signal from mixer 224 is then routed to the adder 222, where it is summed with the other mixed signal from mixer 220 to define a summation signal. The summation signal is then power amplified by a driver 226 and routed to at least one antenna 228.
The transmitter 200 of FIG. 2 utilizes what is referred to as IQ modulation, by virtue of the separate digital-to-analog conversion of both the in-phase and quadrature modulation signals (S2 and S3). IQ modulation is preferred in instances where high modulation bandwidth is to be achieved. However, disadvantages regarding implementation and efficiency under IQ modulation stem from the fact that the in-phase and quadrature modulation signals span respective value ranges having both positive and negative values (i.e., signal polarities). Thus, within an IQ modulation context, the DAC stages require sufficient circuit complexity and operating speed to convert bi-polar input signals. Such requirements can be difficult to achieve, particularly in a mass production environment.
Presently, the most readily employed IQ modulation structures, particularly in a digital implementation, add certain predefined offsets (i.e., biases) before or after the analog-to-digital conversion stage within the respective in-phase and quadrature signal flow paths. An undesirable consequence of this approach is that the advantages and speed of class-B operation no longer exist.